Process for high density split-gate memory cell for flash or EPROM
Patent 5414287 Issued on May 9, 1995. Estimated Expiration Date: 
April 25, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 25, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSelf-aligned split gate EPROM Dual EPROM cells on trench walls with virtual ground buried bit lines Manufacture of a split-gate EPROM cell using polysilicon spacers Split-gate EPROM cell using polysilicon spacers Patent #: 5115288 InventorApplicationNo. 231812 filed on 04/25/1994US Classes:257/316, With additional contacted control electrode257/322, With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction)257/324, Multiple insulator layers (e.g., MNOS structure)257/328, Vertical channel or double diffused insulated gate field effect device provided with means to protect against excess voltage (e.g., gate protection diode)257/330, Gate electrode in groove257/331, Plural gate electrodes or grid shaped gate electrode257/E21.422, With floating gate (EPO)257/E21.693, For vertical channel (EPO)257/E29.128, With insulated gate (EPO)257/E29.304, Charging by tunneling of carriers (e.g., Fowler-Nordheim tunneling) (EPO)438/259Including forming gate electrode in trench or recess in substrateExaminersPrimary: Wojciechowicz, EdwardAttorney, Agent or FirmInternational ClassesH01L 029/68H01L 021/265 AbstractA method and structure for manufacturing a high-density split gate memory cell, for a flash memory or EPROM, is described. Silicon islands are formed from a silicon substrate implanted with a first conductivity-imparting dopant. A first dielectric layer surrounds the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over a portion of the vertical surfaces of the first dielectric layer, and acts as a floating gate for the high density split-gate memory cell. A source region is located in the silicon substrate, and is implanted with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant, and surrounds the base of the silicon islands. A drain region is located in the top of the silicon islands, and is also implanted with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant. A second dielectric layer is formed over the top and side surfaces of the floating gate, and acts as an interpoly dielectric. A second conductive layer is formed over that remaining portion of the vertical surfaces of the first dielectric layer not covered by the first conductive layer, and surrounds the second dielectric layer, whereby the second conductive layer is a control gate.Other References
Field of SearchWith additional contacted control electrodeWith charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction) Multiple insulator layers (e.g., MNOS structure) Vertical channel or double diffused insulated gate field effect device provided with means to protect against excess voltage (e.g., gate protection diode) Gate electrode in groove Plural gate electrodes or grid shaped gate electrode | |
