Patent References 3400371 Method and means for path independent device reservation and reconnection in a multi-CPU and shared device access system Virtually addressed cache Method for managing lock escalation in a multiprocessing, multiprogramming environment Virtual memory cache for use in multi-processing systems Locking control with validity status indication for a multi-host processor system that utilizes a record lock processor and a cache memory for each host processor Multi-processor caches with large granularity exclusivity locking System for selectively registering and blocking requests initiated by optimistic and pessimistic transactions respectively for shared objects based upon associated locks Parallel, distributed optimistic concurrency control certification using hardware filtering Patent #: 5263156 InventorsApplicationNo. 132433 filed on 10/06/1993US Classes:711/152, Memory access blocking710/200ACCESS LOCKINGExaminersPrimary: Kriess, Kevin A.Assistant: Chaki, Kakali Attorney, Agent or FirmInternational ClassG06F 015/16AbstractA method for managing concurrency using a serializing token as a supplement to locks for accessing the same page by different processes and ensuring coherence between data caches and a shared access backing store supporting the processes defined onto multiple processors. A shared lock and a new token are issued by a local lock manager (LLM) and local cache manager (LCM) in response to a page read request from a process. An exclusive lock, an invalidation of all cache resident copies of the page, a cache write through to backing store of the changed page, a copyback of a new token, and lock release are responsive to a page write/update request from a process where the token issued to the process during a prior request matches the token stored with a cache resident copy of the page. Otherwise, a write request fails and the process must first issue a read request to the page of interest.Other References
| |