Self-scheduling parallel computer system and method
Patent 5408658 Issued on April 18, 1995. Estimated Expiration Date: 
April 18, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 18, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDigital computer for executing multiple instruction sets in a simultaneous-interleaved fashion Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor Parallel processor system for processing natural concurrencies and method therefor Patent #: 5021945 InventorsApplicationNo. 730365 filed on 07/15/1991US Classes:712/216, DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION712/21, Multiple instruction, Multiple data (MIMD)712/215Simultaneous issuance of multiple instructionsExaminersPrimary: Chan, Eddie P.Attorney, Agent or FirmForeign Patent References
International ClassesG06F 009/38G06F 015/16 AbstractAn incremental method is described for distributing the instructions of an execution sequence among a plurality of processing elements for execution in parallel. The distribution is based upon anticipated availability times of the needed input values for each instruction as well as the anticipated availability times of each processing element for handling each instruction. A self-parallelizing computer system and method are also described for asynchronously processing the distributed instructions in two modes of execution on a set of processing elements which communicate with each other.Other References
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