Multiprocessor cache examiner and coherency checker
June 30, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesCoherent cache structures and methods Coherent cache structures and methods Integrated scalar and vector processors with vector addressing by the scalar processor Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system Error transition mode for multi-processor system Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode Method and apparatus for dynamic cache line sectoring in multiprocessor systems Shared memory multiprocessor system and method of operation thereof Patent #: 5297265 InventorsAssigneeApplicationNo. 085869 filed on 06/30/1993US Classes:702/117, Of circuit700/90, SPECIFIC APPLICATION, APPARATUS OR PROCESS711/119, Multiple caches711/124, Cross-interrogating711/141, Coherency714/20, Plural recovery data sets containing set interrelation data (e.g., time values or log record numbers)714/21, State validity check714/42Memory or storage device component faultExaminersPrimary: Voeltz, Emanuel T.Assistant: Tran, Dalena Attorney, Agent or FirmInternational ClassesG05B 019/02G06F 013/00 AbstractAn arrangement for a multiprocessor RISC system enables each CPU of the system to test the control logic of its cache by indirectly examining states of the caches and comparing those states to predetermined valid cache states of the system. The arrangement includes a plurality of processes configured to acquire information from selected block entries of the caches. The information is then compared with an array of predetermined valid cache states contained in a state table to detect invalid cache states. A cache examining protocol defines the operational procedures followed by the processes when acquiring and examining the information. | |
