Method of forming a SOI transistor having a self-aligned body contact
June 29, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcess for making high performance silicon-on-insulator transistor with body node to source node connection Method of manufacturing double diffused MOSFET with potential biases Process for making semiconductor-on-insulator device interconnects Manufacturing method for semiconductor device Method of manufacturing SOI semiconductor element Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor Patent #: 5273921 InventorsApplicationNo. 268380 filed on 06/29/1994US Classes:438/151, Having insulated gate257/E21.415, Monocrystalline silicon transistor on insulating substrate, e.g., quartz substrate (EPO)257/E29.281, For preventing kink or snapback effect (e.g., discharging minority carriers of channel region for preventing bipolar effect) (EPO)438/586Combined with formation of ohmic contact to semiconductor regionExaminersPrimary: Hearn, Brian E.Assistant: Nguyen, Tan T. International ClassH01L 021/265AbstractAn SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.Other References
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