Patent ReferencesLogic state analyzer with restart and state occurrence qualification Composite logic analyzer capable of data display in two time-related formats Logic analyzer for a multiplexed digital bus Logic state analyzer with graph of captured trace Logic state analyzer with sequential triggering and restart Timing or logic state analyzer with automatic qualified inferential marking and post processing of captured trace data Logic analyzer having a plurality of sampling channels Increased resolution logic analyzer using asynchronous sampling Oscilloscope-like user-interface for a logic analyzer Third party evavesdropping for bus control Patent #: 5182554 InventorsApplicationNo. 055886 filed on 05/04/1993US Classes:714/47Performance monitoring for fault avoidanceExaminersPrimary: Canney, Vincent P.Attorney, Agent or FirmInternational ClassG06F 011/00AbstractA system is provided for monitoring signals transmitted over one or more optical serial interface channels in an ESCON environment. A formatter card mounts on bus connector in a general purpose tracing tool (GPT) and intercepts optical I/O signals being transmitted between a host processor and, a peripheral device. The signals are decoded into trace data words which are then partitioned into ESCON transaction frames and mapped into a block of GPT frames. The GPT block is stored on the formatter card and transmitted to the GPT when the GPT can accept the data. Data received by the GPT is interleaved with data from other formatter cards attached to other I/O channels (both ESCON and non-ESCON) and is displayed or printed in time-correlated format for analysis. Data can also be stored for later review.Other References
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