Cache system for reducing memory latency times
Patent 5404484 Issued on April 4, 1995. Estimated Expiration Date: 
September 16, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 16, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesLook-ahead instruction fetch control for a cache memory Cache miss facility with stored sequences for data fetching Data preloading method and system for using a buffer Patent #: 5239644 InventorsApplicationNo. 945561 filed on 09/16/1992US Classes:711/133Entry replacement strategyExaminersPrimary: Dixon, Joseph L.Assistant: Nguyen, Hiep T. Foreign Patent References
International ClassG06F 012/12AbstractThe improved cache system reduces the effects of latency times by utilizing a preload instruction inserted by the compiler into the code. The preload instruction is sent sufficiently in advance of the corresponding load instruction to guarantee that the relevant data is in the cache memory when the load instruction is received. In addition, the invention prevents the pollution of the cache with data that will only be used once during the expected lifetime of the data in the cache. This second feature of the invention assures that a large number of references to data that will only be used once does not result in the contents of the cache being replaced with the subsequent need to reload the contents after the data references have been completed. | |
