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Parallel processing apparatus and method capable of switching parallel and successive processing modes

Patent 5404472 Issued on April 4, 1995. Estimated Expiration Date: Icon_subject November 10, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Data processor for concurrent executing of instructions by plural execution units Patent #: 4942525
Issued on: 07/17/1990
Inventor: Shintani, et al.

Inventors

Assignee

Application

No. 149932 filed on 11/10/1993

US Classes:

712/229, Mode switch or change712/206, Of multiple instructions simultaneously712/215Simultaneous issuance of multiple instructions

Examiners

Primary: Harrell, Robert B.

Attorney, Agent or Firm

International Class

G06F 009/445

Foreign Application Priority Data

1989-07-07 JP

Abstract

When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.

Other References

  • David T. Hilja "Reducing the Branch Penalty in Pipe-line Processors," Computer (Jul. 1988) pp. 47-55
  • Miller et al. "Floating-Duplex Decode and Execution of Instructions", IBM Technical Disclosure Bulletin, vol. 23, No. 1, (Jun. 1980) pp. 409-41
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