High-performance insulated-gate field-effect transistor
April 21, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesFabrication technique for integrated circuits Method of making short channel IGFET Method in the manufacture of integrated circuits Process for manufacturing semiconductor BICMOS device Semiconductor devices having superconducting interconnects Double implanted LDD transistor self-aligned with gate Method of making cmos with shallow source and drain junctions LDD transistor process having doping sensitive endpoint etching Bipolar process using selective silicon deposition Semiconductor integrated circuit having CMOS inverters InventorAssigneeApplicationNo. 231344 filed on 04/21/1994US Classes:257/383, Contact of refractory or platinum group metal (e.g., molybdenum, tungsten, or titanium)257/384, Including silicide257/385, Multiple polysilicon layers257/387, Gate electrode overlaps at least one of source or drain by no more than depth of source or drain (e.g., self-aligned gate)257/E21.295, Deposition of layer comprising metal, e.g., metal, alloys, metal compounds (EPO)257/E21.43, Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)257/E21.435, Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)257/E29.155, Multiple silicon layers257/E29.156, Including silicide layer contacting silicon layer (EPO)257/E29.255With field effect produced by insulated gate (EPO)ExaminersPrimary: James, Andrew J.Assistant: Meier, Stephen D. Attorney, Agent or FirmForeign Patent References
International ClassesH01L 029/10H01L 029/68 AbstractAn improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.Other References
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