U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

One chip microcomputer having programmable I/O terminals programmed according to data stored in nonvolatile memory

Patent 5396639 Issued on March 7, 1995. Estimated Expiration Date: Icon_subject March 7, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Microprocessor apparatus
Patent #: 4486827
Issued on: 12/04/1984
Inventor: Shima ,   et al.

Integrated circuit having processor coupled by common bus to programmable read only memory for processor operation and processor uncoupled from common bus when programming read only memory from external device Patent #: 5088023
Issued on: 02/11/1992
Inventor: Nakamura, et al.

Inventors

Assignee

Application

No. 760391 filed on 09/16/1991

US Classes:

712/37, Programmable (e.g., EPROM)712/38Offchip interface

Examiners

Primary: Black, Thomas G.
Assistant: Harrity, Paul

Attorney, Agent or Firm

International Classes

G06F 015/78
G06F 001/24
G06F 003/00

Abstract

A one-chip microcomputer according to the present invention is provided with an initial reset circuit for producing a first initial reset signal having a first reset period and a second initial reset signal having a second reset period which is longer than the first reset period, an access circuit for gaining access to an address in a nonvolatile memory such as a built-in ROM to read data therefrom, and I/O buffer circuits. A storage circuit and an I/O buffer connected to a programmable I/O terminal are provided in the I/O buffer circuit and a function of the I/O terminal with options is selected in conformity with the data set in the storage circuit. The data stored at a predetermined address in the nonvolatile memory is transferred to the storage circuit by operating the access circuit until the termination of the reset period of the second initial reset signal after the termination of the first reset period of the first initial reset signal. With this arrangement, as the contents of write data are altered by writing the data to the nonvolatile memory from the outside, an optional function of the programmable I/O terminal can be selected in accordance with the alteration.

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