Patent ReferencesMicroprocessor apparatus Integrated circuit having processor coupled by common bus to programmable read only memory for processor operation and processor uncoupled from common bus when programming read only memory from external device Patent #: 5088023 InventorsAssigneeApplicationNo. 760391 filed on 09/16/1991US Classes:712/37, Programmable (e.g., EPROM)712/38Offchip interfaceExaminersPrimary: Black, Thomas G.Assistant: Harrity, Paul Attorney, Agent or FirmInternational ClassesG06F 015/78G06F 001/24 G06F 003/00 AbstractA one-chip microcomputer according to the present invention is provided with an initial reset circuit for producing a first initial reset signal having a first reset period and a second initial reset signal having a second reset period which is longer than the first reset period, an access circuit for gaining access to an address in a nonvolatile memory such as a built-in ROM to read data therefrom, and I/O buffer circuits. A storage circuit and an I/O buffer connected to a programmable I/O terminal are provided in the I/O buffer circuit and a function of the I/O terminal with options is selected in conformity with the data set in the storage circuit. The data stored at a predetermined address in the nonvolatile memory is transferred to the storage circuit by operating the access circuit until the termination of the reset period of the second initial reset signal after the termination of the first reset period of the first initial reset signal. With this arrangement, as the contents of write data are altered by writing the data to the nonvolatile memory from the outside, an optional function of the programmable I/O terminal can be selected in accordance with the alteration. | |