System and method for reducing the penalty associated with data cache misses
Patent 5396604 Issued on March 7, 1995. Estimated Expiration Date: 
March 7, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
March 7, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesOrganization of an integrated cache unit for flexible usage in cache system design Digital processor with a four part data register for storing data before and after data conversion and data calculations Copy-back cache system having a plurality of context tags and setting all the context tags to a predetermined value for flushing operation thereof Patent #: 5146603 InventorsApplicationNo. 729132 filed on 07/12/1991US Classes:712/207, Prefetching711/4, Dynamic-type storage device (e.g., disk, tape, drum)711/118, Caching711/126, User data cache712/219Reducing an impact of a stall or pipeline bubbleExaminersPrimary: Coleman, EricInternational ClassG06F 012/00AbstractA computer system having a central processor unit (CPU) with a reduced instruction set, a decoder and a data cache memory, for processing an instruction to retrieve data from a main memory to prevent a data cache miss. The system decodes an instruction requiring the CPU to load a value into a read only general purpose memory register, the instruction thereby indicating to the CPU to perform a prefetch operation and providing information corresponding to an address of the data to be fetched from the main memory. The system processes, substantially simultaneously, further instructions following the load register instruction and the prefetch operation by determining the address in main memory of the data to be prefetched using the information provided by the load instruction, fetching the data from the main memory, and storing the data in the data cache memory to permit accesses to the data and thereby reduce the penalty associated with a data cache miss.Other References
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