Method and apparatus for adaptive clock recovery
Patent 5396492 Issued on March 7, 1995. Estimated Expiration Date: 
April 28, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 28, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3754098 Local area network control system synchronization with phase-lock loop Method and means for transferring a data payload from a first SONET signal to a SONET signal of different frequency Patent #: 5142529 InventorAssigneeApplicationNo. 054332 filed on 04/28/1993US Classes:370/412, Queuing arrangement370/466, Converting between protocols370/517, Including delay device375/371Phase displacement, slip or jitter correctionExaminersPrimary: Safourek, Benedict V.Assistant: Jung, Min Attorney, Agent or FirmInternational ClassH04J 003/06AbstractAn adaptive clock recovery arrangement for deriving a synchronous clock from an asynchronous, packet stream such as an asynchronous transfer mode (ATM) cell stream. The deviation in the magnitude of information stored in a first-in-first-out memory is continually monitored, and the synchronous clock frequency, referred to as the adaptive line clock frequency, is adjusted in a plurality of modes, under the control of a processor. The adjustment is made in response to a detected increasing condition of the monitored deviation. The adjustments are open-loop adjustments made without continually adjusting the adaptive line clock frequency based on the monitored deviation. Damping is substantially reduced compared with "conventional" PLL arrangements because the open-loop adjustments result in a rapid frequency correction with perfect or nearly perfect deadbeat damping, i.e. without the frequency oscillations that continue after the correct frequency is reached in closed-loop arrangements.Other References
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