Patent References 3693155 Partitionable parallel processor Programmable I/O device identification Automatic device selection circuit Access control to a shared resource in an asynchronous system Multicast routing algorithm Modular data routing system Fiber-optic star tree network Method of overlaying virtual tree networks onto a message passing parallel processing network Binary tree parallel processor InventorAssigneeApplicationNo. 994402 filed on 12/21/1992US Classes:709/220, NETWORK COMPUTER CONFIGURING340/825.02, Tree or cascade709/223COMPUTER NETWORK MANAGINGExaminersPrimary: Bowler, Alyssa H.Assistant: An, Meng-Ai T. Attorney, Agent or FirmInternational ClassesG06F 003/00G06F 009/00 G06F 013/00 AbstractA node identification system is described for use in a computer system in which the various components of the system are interconnected via nodes on a communications bus. Once the topology of the nodes has been resolved into an acyclic directed graph, each node may be assigned a non-predetermined unique address. Each node having a plurality of ports has an apriori assigned priority for port selection. Each child node connected to a parent is allowed to respond in the predetermined sequence depending upon the port through which it is connected to its parent. Each node in the graph will announce its presence according to its location in the graph. Each receives an address incremented from the previous addresses assigned, thereby insuring uniqueness. The same mechanism may be implemented to allow each node in turn to broadcast information on the bus concerning the parameters of its local host. Likewise, additional information may be conveyed from each node concerning connections to other nodes thereby allowing a host system to generate a map of the resolved topology including any information about disabled links which may be used for redundancy purposes.Other References
Field of SearchTree or cascade | |