Hardware virtualizer for supporting recursive virtual computer systems on a host computer system
Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations
Method and means for switching system control of CPUs
Fast two-level dynamic address translation method and means
Instruction processing in higher level virtual machines by a real machine
Virtual machine system and method for controlling machines of different architectures
Virtual machine system with address translation buffer for holding host and plural guest entries
Logical resource partitioning of a data processing system
Virtual machine system which translates virtual address from a selected virtual machine into real address of main storage
Apparatus and method for providing private and shared access to host address and data spaces by guest programs in a virtual machine computer system Patent #: 5230069
ApplicationNo. 736022 filed on 07/25/1991
US Classes:718/100, TASK MANAGEMENT OR CONTROL711/203Virtual addressing
ExaminersPrimary: Harvey, Jack B.
Assistant: Whitfield, Michael A.
Attorney, Agent or Firm
Foreign Patent References
International ClassesG06F 012/08
Foreign Application Priority Data1990-07-30 JP
AbstractA level-2 virtual machine is constructed under the control of a level-1 operating system (OS) operating on a real machine (level-1), and a level-3 virtual machine is constructed under the control of another operating system (OS) operating on the level-2 virtual machine. A level-3 virtual address generated in the level-3 virtual machine is translated to a level-2 virtual address, which is further translated to a level-1 virtual address. A third predetermined main storage address is added to the level-1 virtual address to generate a level-1 absolute address. The translated address is checked as to whether it is within a predetermined area on the main storage.