Multimedia storage system with highly compact memory device
November 2, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSingle transistor electrically programmable memory device and method Dual EPROM cells on trench walls with virtual ground buried bit lines Memory cell structure of semiconductor memory device Semiconductor nonvolatile memory Vertical memory cell array and method of fabrication Highly compact EPROM and flash EEPROM devices Electrically erasable and programmable read only memory with trench structure Shadow ram cell having a shallow trench eeprom Patent #: 5196722 InventorApplicationNo. 970728 filed on 11/02/1992US Classes:257/316, With additional contacted control electrode257/320, Separate control electrodes for charging and for discharging floating electrode257/E21.693, For vertical channel (EPO)257/E27.103, Electrically programmable ROM (EPO)257/E29.306, Hot carrier injection from channel (EPO)365/185.26, Floating electrode (e.g., source, control gate, drain)365/185.29EraseExaminersPrimary: Limanek, Robert P.Assistant: Hardy, David B. Attorney, Agent or FirmInternational ClassesH01L 029/06H01L 029/68 AbstractA highly compact nonvolatile solid state memory core is provided that stores and reproduces both digital and analog signals for multimedia applications. The memory core includes vertical electrically erasable and programmable read only memories (EEPROM) cells having, for example, a stacked gate or a split channel configuration. An array of EEPROM cells on the same chip is prewritten and is used as a reference for digital-analog conversions and for memory cell programming. An intelligent write method allows each memory cell to either store an analog signal or multiple digital signals. Based on the previously stored signal, the intelligent write method determines whether to charge or to discharge the floating gate associated with the selected memory cell. Thus, full erasure is not required prior to programming each memory cell. The present invention significantly increases the density of memory cell arrays while prolonging the useful life of the array.Other References
Field of SearchWith floating gate electrodeSeparate control electrodes for charging and for discharging floating electrode With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling Capacitor for signal storage in combination with non-volatile storage means Non-homogeneous composition insulator layer (e.g., graded composition layer or layer with inclusions) With means to facilitate light erasure Plural additional contacted control electrodes With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction) Additional control electrode is doped region in semiconductor substrate With additional, non-memory control electrode or channel portion (e.g., accessing field effect transistor structure) With irregularities on electrode to facilitate charging or discharging of floating electrode With additional contacted control electrode Multiple insulator layers (e.g., MNOS structure) | |
