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Semiconductor chip bonded to a substrate and method of making

Patent 5385869 Issued on January 31, 1995. Estimated Expiration Date: Icon_subject July 22, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Multi-lead frame member with means for limiting mold spread
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Inventor: Hayakawa ,   et al.

Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
Patent #: 4604644
Issued on: 08/05/1986
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Process of producing semiconductor device
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Combination of a support and a semiconductor body and method of manufacturing such a combination
Patent #: 5057458
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Inventor: Hoeberechts, et al.

Ceramic package type semiconductor device and method of assembling the same
Patent #: 5081067
Issued on: 01/14/1992
Inventor: Shimizu, et al.

Method of making a planarized thin film covered wire bonded semiconductor package
Patent #: 5086018
Issued on: 02/04/1992
Inventor: Conru, et al.

Method of using an anisotropically electroconductive adhesive having pressure-deformable electroconductive particles to electrically connect circuits Patent #: 5120665
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Inventors

Assignee

Application

No. 094735 filed on 07/22/1993

US Classes:

29/841, With encapsulating, e.g., potting, etc.257/E21.504, Moulds (EPO)257/E23.125, Substrate forming part of encapsulation (EPO)264/272.17, Semiconductor or barrier layer device (e.g., integrated circuit, transistor, etc.)438/126And encapsulating

Examiners

Primary: Hearn, Brian E.
Assistant: Picardat, Kevin M.

Attorney, Agent or Firm

Foreign Patent References

  • 59-143333 JP 08/13/1984
  • 1161724 JP 06/13/1985
  • 1191456 JP. 08/13/1989
  • 1191457 JP. 08/13/1989

International Class

H01L 021/60

Abstract

A semiconductor chip is flip chip bonded to a substrate having a cavity or a through hole formed therein. The cavity or through hole is preferably large enough to substantially remove the narrow gap which is formed between the portion of the substrate which does not have the cavity or through hole formed therein. This allows for use of mold processes to encapsulate and underfill the semiconductor chip and for line of sight cleaning of the semiconductor chip after bonding.

Other References

  • D. Suryanarayana et al, "Flip Chip Solder Bump Fatigue Life Enhanced by Polymer Encapsulation," 40th Electronic Component Technology Conference Proceedings, 1990, pp. 338-344
  • T. Caulfield et al., "Surface Mount Array Interconnections for High I/O MCM-C to Card Assemblies," 1993 Proceedings of International Conference and Exhibition on Multichip Modules, pp. 320-32
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