Patent ReferencesMulti-lead frame member with means for limiting mold spread Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making Process of producing semiconductor device Hybrid wafer scale microcircuit integration Combination of a support and a semiconductor body and method of manufacturing such a combination Ceramic package type semiconductor device and method of assembling the same Method of making a planarized thin film covered wire bonded semiconductor package Method of using an anisotropically electroconductive adhesive having pressure-deformable electroconductive particles to electrically connect circuits Patent #: 5120665 InventorsAssigneeApplicationNo. 094735 filed on 07/22/1993US Classes:29/841, With encapsulating, e.g., potting, etc.257/E21.504, Moulds (EPO)257/E23.125, Substrate forming part of encapsulation (EPO)264/272.17, Semiconductor or barrier layer device (e.g., integrated circuit, transistor, etc.)438/126And encapsulatingExaminersPrimary: Hearn, Brian E.Assistant: Picardat, Kevin M. Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/60AbstractA semiconductor chip is flip chip bonded to a substrate having a cavity or a through hole formed therein. The cavity or through hole is preferably large enough to substantially remove the narrow gap which is formed between the portion of the substrate which does not have the cavity or through hole formed therein. This allows for use of mold processes to encapsulate and underfill the semiconductor chip and for line of sight cleaning of the semiconductor chip after bonding.Other References
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