Memory cell having a super supply voltage
Patent 5379260 Issued on January 3, 1995. Estimated Expiration Date: 
September 30, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 30, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDynamic semiconductor memory device High speed zero power reset circuit for CMOS memory cells Semiconductor memory device Test apparatus for static-type semiconductor memory devices Static RAM including leakage current detector Semiconductor memory with a circuit for testing characteristics of flip-flops including selectively applied power supply voltages Patent #: 5159571 InventorAssigneeApplicationNo. 128895 filed on 09/30/1993US Classes:365/201, Testing365/154, Flip-flop (electrical)365/156, Complementary365/226, POWERING714/718, Memory testing714/721Electrical parameter (e.g., threshold voltage)ExaminersPrimary: LaRoche, Eugene R.Assistant: Mai, Son Attorney, Agent or FirmInternational ClassG11C 029/00AbstractAccording to the present invention, a static random access memory (SRAM) cell which is normally supplied with a nominal supply voltage under normal operating conditions, may be supplied with a super supply voltage so that tests requiring high voltages and increased current levels, such as diagnostic and reliability "stress" tests may be performed. The super supply voltage is greater in magnitude than the nominal supply voltage, and may range from approximately 7 volts to 13 volts for SRAM cells requiring a positive voltage supply. The super supply voltage level may be controlled by a test mode or by a bond pad using existing power supply circuitry. | |
