Three dimensional famos memory devices and methods of fabricating
Patent 5379255 Issued on January 3, 1995. Estimated Expiration Date: 
December 14, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 14, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDram cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof Patent #: 5001526 InventorAssigneeApplicationNo. 990564 filed on 12/14/1992US Classes:438/267, Including forming gate electrode as conductive sidewall spacer to another electrode257/E21.693, For vertical channel (EPO)257/E27.103, Electrically programmable ROM (EPO)257/E29.304, Charging by tunneling of carriers (e.g., Fowler-Nordheim tunneling) (EPO)257/E29.306, Hot carrier injection from channel (EPO)365/182, Insulated gate devices365/185.06, Segregated columns365/185.16, Virtual ground365/185.18, Particular biasing365/185.26, Floating electrode (e.g., source, control gate, drain)365/185.28, Tunnel programming365/185.3, Over erasure365/185.33, Flash438/259, Including forming gate electrode in trench or recess in substrate438/265, Oxidizing sidewall of gate electrode438/266Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.)ExaminersPrimary: Nguyen, Viet Q.Attorney, Agent or FirmForeign Patent References
International ClassesH01L 029/78H01L 027/10 AbstractMemory cell transistors are provided in which pillar structures or column structures (12, 12a, 14, and 14a) are formed at the face of a semiconductor substrate (10). Floating gates (46) and control gates (52) are formed adjacent to the pillar structures or column structures (12, 12a, 14, and 14a). The floating gates (46) and control gates (52) are insulatively disposed by gate oxide layer (42) and insulating layer (50). Source regions (36, 40, and 48) are implanted in the semiconductor substrate (10). Drain regions (38) are also implanted in the pillar structures or column structures (12, 12a, 14 and 14a).Other References
Field of SearchInsulated gate devices | |
