Phase detector and methodology
Patent 5376847 Issued on December 27, 1994. Estimated Expiration Date: 
December 30, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 30, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDigital phase detector Digital phase comparator circuit Phase comparator Phase comparators Phase detector suitable for use in phase lock loop Digital phase comparator for use in a phase lock loop Patent #: 5124594 InventorAssigneeApplicationNo. 998474 filed on 12/30/1992US Classes:327/12, With logic or bistable circuit327/3, Comparison between plural inputs (e.g., phase angle indication, lead-lag discriminator, etc.)327/24Edge sensingExaminersPrimary: Callahan, Timothy P.Assistant: Tran, Toan Attorney, Agent or FirmInternational ClassesH03K 009/06G01R 025/00 AbstractIn one embodiment, a method of providing phase detection from a circuit having first and second inputs and at least one output is disclosed. The method includes a cyclical operation of four steps. The first step awaits the receipt at the first input of an input signal which at least meets the requirements of one of two given binary values. The second step awaits the receipt at the first input of an input signal which at least meets the requirements of the other of the two given binary values before providing an output signal of a first value at the output. The third step awaits the receipt at the second input of an input signal which at least meets the requirements of one of two given binary values. The fourth step awaits the receipt at the second input of an input signal which at least meets the requirements of the other of the two given binary values before changing the output signal at the output to a second value. The process then returns to the first step. Apparatus in accordance with the inventive method are also described, including preferred TTL and CMOS logic diagrams for implementing a four state machine.Field of SearchDIGITAL COMPARATOR SYSTEMS | |
