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Process of making pad structure for solder ball limiting metallurgy having reduced edge stress

Patent 5376584 Issued on December 27, 1994. Estimated Expiration Date: Icon_subject December 31, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Method of forming a solder interconnection capable of sustained high power levels between a semiconductor device and a supporting substrate
Patent #: 4360142
Issued on: 11/23/1982
Inventor: Carpenter ,   et al.

Solder mound formation on substrates
Patent #: 4434434
Issued on: 02/28/1984
Inventor: Bhattacharya ,   et al.

Compressively stresses titanium metallurgy for contacting passivated semiconductor devices
Patent #: 4514751
Issued on: 04/30/1985
Inventor: Bhattacharya

Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate
Patent #: 5027188
Issued on: 06/25/1991
Inventor: Owada, et al.

Method of forming metal contact pads and terminals on semiconductor chips
Patent #: 5137845
Issued on: 08/11/1992
Inventor: Lochon, et al.

Etching processes for avoiding edge stress in semiconductor chip solder bumps
Patent #: 5268072
Issued on: 12/07/1993
Inventor: Agarwala, et al.

Method of manufacturing semiconductor device terminal having a gold bump electrode Patent #: 5298459
Issued on: 03/29/1994
Inventor: Arikawa, et al.

Inventor

Assignee

Application

No. 998982 filed on 12/31/1992

US Classes:

438/614, Plural conductive layers216/100, Substrate contains elemental metal, alloy thereof, or metal compound257/737, Bump leads257/738, Ball shaped257/780, Ball or nail head type contact, lead, or bond257/E21.508, Forming solder bumps (EPO)438/615Including fusion of conductor

Examiners

Primary: Chaudhuri, Olik
Assistant: Pham, Long

Attorney, Agent or Firm

Foreign Patent References

  • 0018446 JP 02/13/1981
  • 0049543 JP 05/13/1981
  • 0117135 JP 07/13/1984
  • 1120038 JP 05/13/1989
  • 1120848 JP 05/13/1989
  • 0082623 JP 03/13/1990
  • 3044935 JP 02/13/1991

International Class

H01L 021/44

Abstract

A two-step masking process is disclosed for forming a ball limiting metallurgy (BLM) pad structure for a solder joint interconnection used between a support substrate and a semiconductor chip. A solder non-wettable layer and a solder wettable layer are deposited on the surface of a support substrate or semiconductor chip which are to be connected. A phased transition layer is deposited between the wettable and non-wettable layers. A thin photo-resist mask defines an area of the solder wettable and phased layers which are etched to form a raised, wettable frustum cone portion. A second mask is deposited on the surface of the support substrate or semiconductor chip, and has an opening concentrically positioned about the frustum cone. Solder is deposited in the opening and covers the frustum cone and the area about its periphery. When solidified, the solder, acting as a mask, is used to sub-etch the underlying solder non-wettable layer thereby defining the BLM pad. When reflowed, the solder beads away from the surface of the solder non-wettable layer to form a ball which securely adheres about the frustum cone.

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