Apparatus and method for optimizing performance of a cache memory in a data processing system
Patent 5375216 Issued on December 20, 1994. Estimated Expiration Date: 
February 28, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
February 28, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3858182 Hierarchical memory system including separate cache memories for storing data and instructions Method and apparatus for simultaneously decoding three operands in a variable length instruction when one of the operands is also of variable length Method of transferring burst data in a microprocessor Patent #: 5255378 InventorsAssigneeApplicationNo. 844011 filed on 02/28/1992US Classes:711/123User data cache and instruction data cacheExaminersPrimary: Dixon, Joseph L.Assistant: Nguyen, Hiep T. Attorney, Agent or FirmInternational ClassG06F 012/02AbstractA circuit for allowing greater user control over a cache memory is implemented in a data processor (20). Cache control instructions have been implemented to perform touch load, flush, and allocate operations in data cache (54) of data cache unit (24). The control instructions are decoded by both instruction cache unit (26) and sequencer (34) to provide necessary control and address information to load/store unit (28). Load/store unit (28) sequences execution of each of the instructions, and provides necessary control and address information to data cache unit (24) at an appropriate point in time. Cache control logic (60) subsequently processes both the address and control information to provide external signals which are necessary to execute each of the cache control instructions. Additionally, cache control logic (60) provides an external transfer code signal which allows a user to know when a cache transaction is performed.Other References
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