Computer with main memory and cache memory for employing array data pre-load operation utilizing base-address and offset operand
Patent 5371865 Issued on December 6, 1994. Estimated Expiration Date: 
December 6, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 6, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesHierarchical data store with look-ahead action Data processing system having a high speed buffer memory Apparatus and method for controlling storage access in a multilevel storage system Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements Streamlined instruction processor Patent #: 4926323 InventorsAssigneeApplicationNo. 715932 filed on 06/14/1991US Classes:711/125Instruction data cacheExaminersPrimary: Robertson, David L.Assistant: Kim, Matthew Attorney, Agent or FirmForeign Patent References
International ClassesG06F 012/02G06F 012/08 Foreign Application Priority Data1990-06-14 JPAbstractA computer having a main memory for storing a plurality of data, a cache memory for temporarily storing a portion of the plurality of data, a processor for accessing data stored in the cache memory and processing the data according to instructions. The processor has an access instruction combined with a preload instruction, and an access instruction only for accessing data, and includes indicator circuitry for indicating a preload condition to the cache memory when the processor accesses data from the cache memory according to the access instruction combined with the preload instruction. The cache memory preloads data to be accessed next by the processor from the main memory when the processor indicates the preload condition.Other References
| |
