Nand cell type programmable read-only memory with common control gate driver circuit
Electrically erasable programmable read-only memory with NAND cellstructure
Apparatus for providing block erasing in a flash EPROM
Semiconductor integrated circuit Patent #: 5241510
ApplicationNo. 027489 filed on 03/05/1993
US Classes:365/185.11, Bank or block architecture365/185.17, Logic connection (e.g., NAND string)365/185.18, Particular biasing365/185.22, Verify signal365/185.27, Substrate bias365/218, Erase365/230.03, Plural blocks or banks365/230.08Including particular address buffer or latch circuit arrangement
ExaminersPrimary: LaRoche, Eugene R.
Assistant: Mai, Son
Attorney, Agent or Firm
Foreign Patent References
International ClassesG11C 011/34
Foreign Application Priority Data1992-03-05 JP
AbstractIn response to a plurality of address signal input from the outside in sequence, an erase information inputting section controls an erase information holding section corresponding to the batch erase block to be erased so as to hold an erase information data. By repeating this operation in sequence, the erase information data are stored in the erase information holding sections corresponding to the plural batch erase blocks to be erased. Successively, on the basis of the erase information data stored in the erase information holding sections, block erasing sections are activated to erase all the nonvolatile memory cells of each of the corresponding blocks where the erase information data are held. As a result, the erasure operation is achieved for all the batch erase blocks corresponding to the erase information holding sections in each of which the erase information data is held, so that a plurality of batch erase blocks can be erased simulataneously, thus reducing the erasure time, as compared with the prior art memory device.