Method and apparatus for achieving multilevel inclusion in multilevel cache hierarchies
May 27, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesThree level memory hierarchy using write and share flags Second level cache replacement method and apparatus Set associative sector cache Interleaved set-associative memory Hierarchical cache memory system and method Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory Digital computer with multisection cache High speed buffer store arrangement for quick wide transfer of data Cache hierarchy design for use in a memory management unit Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage InventorAssigneeApplicationNo. 068294 filed on 05/27/1993US Classes:711/122Hierarchical cachesExaminersPrimary: Dixon, Joseph L.Assistant: Kim, Matthew Attorney, Agent or FirmInternational ClassG06F 012/08AbstractA method for achieving multilevel inclusion in a computer system with first and second level caches. The caches align on a "way" basis by their respective cache controllers communicating with each other which blocks of data they are replacing and which of their cache ways are being filled with data. On first and second level cache read misses the first level cache controller provides way information to the second level cache controller to allow received data to be placed in the same way. On first level cache read misses and second level cache read hits, the second level cache controller provides way information to the first level cache controller, which places data in the indicated way. On processor writes the first level cache controller caches the writes and provides the way information to the second level cache controller which uses the way information to select the proper way for data storage. An inclusion bit is set on data in the second level cache that is duplicated in the first level cache. On a second level cache snoop hit, the second level cache controller checks the respective inclusion bit to determine if a copy of this data also resides in the first level cache. The first level cache controller is directed to snoop the bus only if the respective inclusion bit is set.Other References
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