U.S. patents available from 1976 to present.
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Programmable logic device with redundant circuitry

Patent 5369314 Issued on November 29, 1994. Estimated Expiration Date: Icon_subject February 22, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

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Embossed decorative facing panel
Patent #: 3955261
Issued on: 05/11/1976
Inventor: Appel ,   et al.

Programmable arrays
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Issued on: 04/26/1977
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Redundant rows in integrated circuit memories
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Parallel-shift error reconfiguration
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Semiconductor memory with redundant column circuitry
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Issued on: 09/01/1987
Inventor: Anderson

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Patent #: 4706216
Issued on: 11/10/1987
Inventor: Carter

Semiconductor device with redundancy circuit and means for activating same
Patent #: 4791319
Issued on: 12/13/1988
Inventor: Tagami ,   et al.

Logic redundancy circuit scheme
Patent #: 4798976
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Inventor: Curtin ,   et al.

Redundancy system with distributed mapping
Patent #: 4800302
Issued on: 01/24/1989
Inventor: Marum

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Inventors

Application

No. 199620 filed on 02/22/1994

US Classes:

326/13, With field effect-transistor326/39, Array (e.g., PLA, PAL, PLD, etc.)326/44Field effect transistor

Examiners

Primary: Hudspeth, David

Attorney, Agent or Firm

International Class

H03K 019/177

Abstract

A programmable logic device is provided that has redundant circuitry. When a portion of the programmable logic device circuitry is found to be defective, the redundant circuitry is switched into use in place of the defective circuitry by programming appropriate portions of the circuitry of the programmable logic device. The programmable logic device is arranged in rows and columns of programmable logic containing logic array blocks, which a user selectively configures by loading programming data into vertical and horizontal programming blocks. Programming blocks are used to program the logic array blocks and various associated logic circuitry. When the redundant circuitry is switched into place, the programming data is redirected to the appropriate programming blocks, so that the device functions identically, regardless of whether or not the redundant circuitry is used.

Other References

  • Recent Developments in Switching Theory, A. Mukhopadhyay, ed., Academic Press, N.Y., 1971, chapters VI and IX, pp. 229-254 and 369-422
  • K. Kokkonen et al., "Memories and Redundancy Techniques", Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 80-1, Feb., 1981
  • J. Bindels et al., "Cost-effective Yield Improvement in Fault-tolerant VLSI Memory", Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 82-3, Feb., 1981
  • S. Eaton et al., "A 100ns 64K Dynamic RAM using Redundancy Techniques", Digest of Technical Papers, IEEE International Solid-State Circuits Confernece, pp. 84-5, Feb., 1981
  • F. Hatori et al., "Introducing Redundancy in Field Programmable Gate Arrays", Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, pp. 7.1.1-7.1.4, May, 1993
  • Preliminary Data booklet for Altera 32 Macrocell High Density Max EPLD EPM5032, 1988, Altera Corporation, Santa Clara (now San Jose), Calif
  • "Programmable Logic Devices with Spare Circuits for Use in Replacing Defective Circuits
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