Circuits and methods for multiple control in data processing systems
Shared resource locking apparatus
Hierarchical multiple bus computer architecture
Shared computer resource allocation system having apparatus for informing a requesting computer of the identity and busy/idle status of shared resources by command code
Bus device which performs protocol confidential transactions Patent #: 5148545
ApplicationNo. 766784 filed on 09/27/1991
US Classes:709/210, Slave computer locking370/402, Bridge between bus systems370/466, Converting between protocols709/208, MASTER/SLAVE COMPUTER CONTROLLING709/230, COMPUTER-TO-COMPUTER PROTOCOL IMPLEMENTING709/246, COMPUTER-TO-COMPUTER DATA MODIFYING710/315Different protocol (e.g., PCI to ISA)
ExaminersPrimary: Bowler, Alyssa H.
Assistant: Shah, Alpesh M.
Attorney, Agent or Firm
International ClassG06F 013/00
AbstractA bus-to-bus interface preserves data coherence between masters and slaves operating within a multiple processor computer system. Two buses are connected via the interface. The first bus connects a number of self-identifying masters. The second bus connects a number of master devices and a number of slave devices. The second bus has no mechanism with which devices connected to the second bus may identify themselves. The interface contains a pair of registers for each slave device connected through the second bus. One register stores a busy bit if the corresponding slave is engaged on behalf of a master. The second register stores an identifying code for the master delegating a task to the corresponding slave. When a slave has accepted a task on behalf of a master and commanded the master to relinquish the bus, the busy register will be set and the master identification register will store the identifying code for the delegating master. Thereafter no master will be permitted to access the engaged slave unless the master identification code is that of the delegating master. Moreover, a delegating master will be denied access to the slave by that slave until the slave has completed the task accepted on behalf of the master. By preventing unintended masters from accessing slaves prior to the delegating master, inadvertent data transferred to the wrong master is avoided. Data coherence between master and slave is thereby ensured.