Asynchronous signal extracting circuit
Patent 5367545 Issued on November 22, 1994. Estimated Expiration Date: 
March 4, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
March 4, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesQuasi-pulse stuffing synchronization Network multiplex structure Device for reducing jitter caused by pointer adjustments in a digital telecommunication network Patent #: 5245636 InventorsApplicationNo. 838230 filed on 03/04/1992US Classes:375/372, Elastic buffer375/376Phase locked loopExaminersPrimary: Bocure, TesfaldetForeign Patent References
International ClassH04L 007/027Foreign Application Priority Data1990-07-04 JPAbstractAn asynchronous signal extracting circuit for extracting asynchronous signals multiplexed in a synchronization frame, including a demultiplexer unit that demultiplexes asynchronous signals and clock signals which are in synchronism with valid data in the asynchronous signals, a buffer memory that writes valid data in the demultiplexed asynchronous signals using the clock signals as write clock signals, a phase-locked loop circuit that forms read clock signals for the memory, and a control unit that switches the frequency band of a low-pass filter in the circuit periodically or in response to a detection signal of pointer adjustment. The circuit suppresses low-frequency jitter contained in the read clock signals.Other References
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