Method for constructing a dual sided, wire bonded integrated circuit chip package
October 13, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor device package with dies mounted on both sides of the central pad of a metal frame Method of making a memory device by packaging two integrated circuit dies in one package Method of manufacturing an electronic circuit component incorporating a heat sink Three-dimensional memory card structure with internal direct chip attachment Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film Patent #: 5273938 InventorsApplicationNo. 135732 filed on 10/13/1993US Classes:29/827, Beam lead frame or beam lead device257/E21.502, Encapsulation, e.g., encapsulation layer, coating (EPO)257/E23.052, Assembly of semiconductor devices on lead frame (EPO)438/107, Assembly of plural semiconductive substrates each possessing electrical device438/118, Including adhesive bonding step438/123Lead frameExaminersPrimary: Hearn, Brian E.Assistant: Picardat, Kevin M. Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/60AbstractA method for constructing a dual sided integrated circuit chip package. A leadframe is formed comprising a set of die pads, and a set of lead fingers corresponding to each die pad. An integrated circuit die is disposed onto a first side and a second side of each die pad. Each integrated circuit die is wire bonded to the corresponding lead fingers. The temperature during the second side die attach and wire bonding steps is controlled and/or compatible materials are selected to prevent warping of the leadframe, and special steps are also implemented to eliminate mold flash, plastic mold cracking and overcuring and increasing the adhesion. | |
