Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
December 11, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesVariable function programmed calculator Computing system with multifunctional arithmetic logic unit in single integrated circuit Dynamically reprogrammable array logic system Current source which saves power in programmable logic array circuitry Dynamically reconfigurable array logic Writable logic array Programmable integrated circuit micro-sequencer device Configurable electrical circuit having configurable logic elements and configurable interconnects Programmable logic array having a changeable logic structure Switching array with concurrent marking capability InventorApplicationNo. 989236 filed on 12/11/1992US Classes:712/1PROCESSING ARCHITECTUREExaminersPrimary: Bowler, Alyssa H.Assistant: Harrity, John Attorney, Agent or FirmInternational ClassG06F 015/31AbstractAn integrated circuit computing device is comprised of a dynamically configurable Field Programmable Gate Array (FPGA). This gate array is configured to implement a RISC processor and a Reconfigurable Instruction Execution Unit. Since the FPGA can be dynamically reconfigured, the Reconfigurable Instruction Execution Unit can be dynamically changed to implement complex operations in hardware rather than in time-consuming software routines. This feature allows the computing device to operate at speeds that are orders of magnitude greater than traditional RISC or CISC counterparts. In addition, the programmability of the computing device makes it very flexible and hence, ideally suited to handle a large number of very complex and different applications.Other References
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