Data processing and communication
March 15, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3676852 Parallel access computer memory system employing a power-of-two memory modules Method of processing an operating system in a multi-processor system Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and data processing Method for retrieving and updating data in a real-time data base system Interprocess communication queue location transparency Wormhole communications arrangement for massively parallel processor Message-driven processor in a concurrent computer Dynamic routing system for a multinode communications network Massively parallel processor including transpose arrangement for serially transmitting bits of data words stored in parallel InventorAssigneeApplicationNo. 031930 filed on 03/15/1993US Classes:709/243, Decentralized controlling709/234, Data flow compensating719/314Message using queueExaminersPrimary: Cosimano, Edward R.Attorney, Agent or FirmForeign Patent References
International ClassG06F 015/20Foreign Application Priority Data1988-01-15 GBAbstractA data processing system having a plurality of processing units (C1, C2), a plurality of memory units (M1, M2) and a communication system providing communication between the processing units and the memory units. The processing units each have a plurality of register sets (R1, R2) allowing them to run a plurality of processes. When a process requires data from memory, which it receives over the communication system, its respective processing unit processes another of its processes until that requires data. Data is transmitted over the communication system, which may be configured as a grid, in the form of packets. The grid is configured from routing devices which include first-in-first-out devices for the buffering of packets. The system facilitates the construction of circuits integrated onto a singel wafter of semiconducting material. Furthermore the grid structure may also be employed as a local area network and computers having a similar architecture may be connected to the network providing a processing facility of considerable power.Other References
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