Patent ReferencesDigital duplex transmission system Bit-by-bit time-division digital switching network Bit-by-bit time-division switching network Group coding system for serial data transmission Method of efficiently and simultaneously transmitting both isochronous and nonisochronous data in a computer network Method of simultaneously transmitting isochronous and nonisochronous data on a local area network Method of inserting and removing isochronous data into a sequence of nonisochronous data characters without slot allocation on a computer network Multiplexed digital packet telephone system Computer communications subsystem using an embedded token-passing network Distributed switching system InventorsApplicationNo. 970329 filed on 11/02/1992US Classes:370/445, Carrier sense multiple access (CSMA)341/102, To or from "N" out of "M" codes370/458, Using time slots370/501RepeaterExaminersPrimary: Hsu, Alpus H.Attorney, Agent or FirmInternational ClassesH03M 007/00H04J 003/02 AbstractA network for transferring packet data in a frame structure, preferably mixed with isochronous data is provided. The frame structure is a continuously repeating structure, with each frame having a number of time slots. Certain ones of the time slots are available for transmitting packet data. The packet data is re-timed, e.g., by using a FIFO to output the data nibble-wise as required by the frame structure. Similar re-timing can be used for isochronous data so that the frame structure defines time-division multiplexing of the packet data and isochronous data. A four/five encoding scheme provides sufficient encoding efficiency that both the packet data and other data can be accommodated without degrading the data rate of the packet data. The encoding scheme provides extra symbols which can be used for transferring "no carrier" information, or "frame alignment" messages. Preferably, the frame structure is translated to and from a packet structure to permit the present invention to be used with previously available packet circuitry such as a media access controller and a hub repeater circuit. Latency of the FIFO can be reduced by pre-filling with packet preambles, and/or sub-latency propagation of preamble bytes, or providing special MACs which do not output preambles, and using the buffer circuitry to output preambles.Other References
Field of SearchAdaptive codingTo or from particular bit symbol To or from packed format To or from variable length codes To or from NRZ (nonreturn-to-zero) codes To or from bi-phase level code (e.g., split phase code, Manchester code) To or from differential codes Byte length changed To or from "N" out of "M" codes | |