Electrically erasable memory with self-limiting erase
Non-volatile semiconductor memory device erasing operation
Apparatus for providing block erasing in a flash EPROM
Single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate
Erase circuitry for a non-volatile semiconductor memory device
Electrically page erasable and programmable read only memory
Nonvolatile memory cell
Method and apparatus for erasing an array of electrically erasable EPROM cells
Methods of repairing field-effect memory cells in an electrically erasable and electrically programmable memory device Patent #: 5233562
ApplicationNo. 069327 filed on 06/01/1993
US Classes:365/185.12, Parallel row lines (e.g., page mode)365/185.26, Floating electrode (e.g., source, control gate, drain)365/185.3, Over erasure365/185.33Flash
ExaminersPrimary: LaRoche, Eugene R.
Assistant: Nguyen, Tan T.
Attorney, Agent or Firm
International ClassG11C 011/34
AbstractA flash EEPROM array (22) is erased and a threshold voltage distribution of the erased flash EEPROM cells (36, 39-46) is converged to within a predetermined voltage range by using a two-step erasing procedure. In the first step, flash EEPROM array (22) is electrically bulk erased using a conventional bulk erase procedure. Electrons are tunneled from the floating gate (38) to the source, causing cells (36, 39-46) to have a relatively low threshold voltage. In the second step, the threshold voltage distribution of the array (22) is converged to within the predetermined voltage range by grounding the source and drain of each cell (36, 39-46), while concurrently applying a high positive voltage to the control gate (27) of each cell (36, 39-46). Some electrons are tunneled back to the floating gate (38), thus converging the threshold voltage distribution to within a predetermined range.
Field of SearchErase