U.S. patents available from 1976 to present.
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Discrete cosine transform circuit

Patent 5357453 Issued on October 18, 1994. Estimated Expiration Date: Icon_subject December 30, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Orthogonal transform processor
Patent #: 4760543
Issued on: 07/26/1988
Inventor: Ligtenberg ,   et al.

Two-dimensional discrete cosine transform processor
Patent #: 4791598
Issued on: 12/13/1988
Inventor: Liou ,   et al.

High speed cosine transform
Patent #: 4829465
Issued on: 05/09/1989
Inventor: Knauer

Discrete cosine transform circuit suitable for integrated circuit implementation
Patent #: 5181183
Issued on: 01/19/1993
Inventor: Miyazaki

DCT/IDCT processor and data processing method
Patent #: 5249146
Issued on: 09/28/1993
Inventor: Uramoto, et al.

Orthogonal transformation processor for compressing information
Patent #: 5268853
Issued on: 12/07/1993
Inventor: Tanaka, et al.

Multiplyless discrete cosine transform Patent #: 5285402
Issued on: 02/08/1994
Inventor: Keith

Inventors

Assignee

Application

No. 175504 filed on 12/30/1993

US Classes:

708/402Discrete Cosine Transform (i.e., DCT)

Examiners

Primary: Mai, Tan V.

Attorney, Agent or Firm

International Class

G06F 015/332

Foreign Application Priority Data

1992-12-30 KR

Abstract

A discrete cosine transform circuit including a shuffle circuit with n (n is an integer) shuffle stages, the n shuffle stages sequentially having 2n, 2n-1, . . . , 21 input/output stages in such a manner that a first one of the n shuffle stages has the 2n input/output stages and a nth one of the n shuffle stages has the 21 input/output stages, the nth shuffle stage including first and second RACs for performing a discrete cosine transform using a distributed arithmetic process, the first RAC having 2n-2 input/output stages, the second RAC having 2n-1 input/output stages. A path switching section is connected to the input stages of the shuffle circuit for changing a transfer path of output information from the output stages of the shuffle circuit according to whether the discrete cosine transform to be processed is a forward discrete cosine transform or an inverse discrete cosine transform. A first selection section is connected to the input stages of the first RAC and a second selection section is connected to the input stages of the second RAC. The first and second selection sections select information according to whether the discrete cosine transform to be processed is the forward discrete cosine transform or the inverse discrete cosine transform and apply the selected information to the first and second RACs, respectively.

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