Logic system of logic networks with programmable selected functions and programmable operational controls
Patent 5357152 Issued on October 18, 1994. Estimated Expiration Date: 
November 10, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 10, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References Re34363 Reprogrammable control circuit Data selection matrix Semiconductor logic device having two-dimensional logic arrays and logic cell chains alternately arranged Semicustom made integrated circuit equipped with controller for input/output buffers Configurable cellular array Patent #: 5243238 InventorsAssigneeApplicationNo. 974237 filed on 11/10/1992US Classes:326/39, Array (e.g., PLA, PAL, PLD, etc.)708/653BinaryExaminersPrimary: Westin, Edward P.Assistant: Roseen, Richard Attorney, Agent or FirmInternational ClassesH03K 019/173H03K 019/086 AbstractA logic system comprising one or more logic networks that can perform a variety of preconfigured or preconfiguarable logic functions. Each logic network is functionally separate from but operatively associated with one or more programmable circuits from which the logic network receives various logic signals. A first logic signal selects or preconfigures the desired logic function to be performed by the or each logic network while a second logic signal controls the operation of the selected logical function. The first logic signal can select a particular logic function to be performed by the logic network based on the contents of programmable cells in the network that are separate from the programmable circuits that supply the logic signals. Alternatively, the first logic signals can switch between various sub-networks each dedicated to performance of a preconfigured logic function. In this manner, the programmable circuit can essentially be dedicated to selecting which of various predetermined logic functions is to be utilized and is relieved of significant functional overhead associated with data manipulation. This can permit a smaller size programmable logic, gate or memory array to be used to control a logic operation of a given complexity, or a given size of array to control more complex operations. Both the programmable circuit(s) and the logic network(s) can be integrated in a single semiconductor chip.Other References
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