Semi-flash A/D converter using switched capacitor comparators
Patent 5355135 Issued on October 11, 1994. Estimated Expiration Date: 
October 11, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 11, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesAnalog to digital converter having a high speed subtraction circuit Flash analog to digital converter Charging circuit for a reference capacitor Analog-to-digital conversion system Adaptive range/DC restoration circuit or use with analog to digital convertors Patent #: 4827191 InventorAssigneeApplicationNo. 304963 filed on 01/30/1989US Classes:341/156, Coarse and fine conversions341/159, Parallel type341/172Using charge transfer devices (e.g., charge coupled devices, charge transfer by switched capacitances)ExaminersPrimary: Logan, Sharon D.Attorney, Agent or FirmInternational ClassesH03M 001/36H03M 001/44 H03M 001/50 AbstractComparators for use in a semi-flash analog-to-digital converter utilize switched capacitor inputs for effecting a subtraction of charge corresponding to the subtraction of voltages to obtain the most significant bit comparisons and least significant bit comparisons. In a preferred embodiment, a 6-input switched-capacitor comparator is employed in which an analog input signal, a most significant reference TAP, and the output from a digital-to-analog converter are sequentially coupled through a first capacitor to the input of an inverting amplifier. A second plurality of input terminals sequentially connects one-half the least significant bit reference potential, 0 volts, and a least significant reference voltage TAP through second capacitive means to the input of the inverting amplifier. One comparator can thereby perform both a most significant bit comparison and a least significant bit comparison in a semi-flash mode of operation. | |
