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Method and apparatus for organizing and analyzing timing information

Patent 5353433 Issued on October 4, 1994. Estimated Expiration Date: Icon_subject October 4, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Simulator system for logic design validation
Patent #: 4527249
Issued on: 07/02/1985
Inventor: Van Brunt

Method for the modeling and fault simulation of complementary metal oxide semiconductor circuits
Patent #: 4763289
Issued on: 08/09/1988
Inventor: Barzilai ,   et al.

Aiding the design of an operation having timing interactions by operating a computer system
Patent #: 4965758
Issued on: 10/23/1990
Inventor: Sherman

Method and apparatus for verifying timing during simulation of digital circuits
Patent #: 5095454
Issued on: 03/10/1992
Inventor: Huang

High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs
Patent #: 5126966
Issued on: 06/30/1992
Inventor: Hafeman, et al.

System which directionally sums signals for identifying and resolving timing inconsistencies Patent #: 5212783
Issued on: 05/18/1993
Inventor: Sherman

Inventor

Assignee

Application

No. 578723 filed on 09/06/1990

US Classes:

713/600CLOCK CONTROL OF DATA PROCESSING SYSTEM, COMPONENT, OR DATA TRANSMISSION

Examiners

Primary: Shaw, Dale M.
Assistant: Dinh, D.

Attorney, Agent or Firm

International Class

G06F 015/60

Abstract

A method and apparatus for analyzing signal timing requirements in complex electronic systems. The invention accepts from the user a set of specifications that express timing constraints, and generates therefrom a set of self-consistent "dependences" that relate signal locations to one another in terms of the minimum or maximum time that must elapse between such locations. The invention also generates signal pattern information that establishes the states of the various signals involved at different relevant times, and can be used to produce a signal profile.

Other References

  • Kara et al., "Antonate Timing Design", IEEE Design & Text of Computers, 1988 pp. 28-40
  • Sherman, Steven, "Algorithms for Timing Requirement Analysis and Generation", ACM/IEEE paper 43.6, 1988 pp. 724-727
  • McWilliams, Verification Of Timing Constraints On Large Digital Systems (Ph.D. Thesis submitted May 1980)
  • Jahanian & Mok, A Graph-Theoretic Approach For Timing Analysis And Its Implementation (1987)
  • Dasarathy, Timing Constraints Of Real-Time Systems: Constructs For Expressing Them, Methods Of Validating Them (1985)
  • Bartlett, Cohen, DeGeus & Hachtel, Synthesis And Optimization Of Multi-Level Logic Under Timing Constraints (1985)
  • Camposano & Kunzmann, Considering Timing Constraints In Synthesis From A Behavioural Description (1986)
  • Alali & Landrault, SIMFLO: A Symbolic Simulation For Timing Constraints Verification (publication date unknown
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