Simulator system for logic design validation
Method for the modeling and fault simulation of complementary metal oxide semiconductor circuits
Aiding the design of an operation having timing interactions by operating a computer system
Method and apparatus for verifying timing during simulation of digital circuits
High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs
System which directionally sums signals for identifying and resolving timing inconsistencies Patent #: 5212783
ApplicationNo. 578723 filed on 09/06/1990
US Classes:713/600CLOCK CONTROL OF DATA PROCESSING SYSTEM, COMPONENT, OR DATA TRANSMISSION
ExaminersPrimary: Shaw, Dale M.
Assistant: Dinh, D.
Attorney, Agent or Firm
International ClassG06F 015/60
AbstractA method and apparatus for analyzing signal timing requirements in complex electronic systems. The invention accepts from the user a set of specifications that express timing constraints, and generates therefrom a set of self-consistent "dependences" that relate signal locations to one another in terms of the minimum or maximum time that must elapse between such locations. The invention also generates signal pattern information that establishes the states of the various signals involved at different relevant times, and can be used to produce a signal profile.