Method and apparatus for concurrency of bus operations
October 2, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesRemote distributed interrupt control for computer peripherals Access control method for multiprocessor systems Distributed arbitration apparatus and method for shared bus Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation System for fast selection of non-cacheable address ranges using programmed array logic Apparatus and method for a synchronous, high speed, packet-switched bus Multiport cache memory control unit including a tag memory having plural address ports and a snoop address part Patent #: 5228135 InventorsAssigneeApplicationNo. 955477 filed on 10/02/1992US Classes:710/310, Buffer or que control711/115Detachable memoryExaminersPrimary: MacDonald, Allen R.Assistant: Auve, Glenn A. Attorney, Agent or FirmForeign Patent References
International ClassG06F 013/00AbstractA method and apparatus for performing concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency. A plurality of CPU boards are coupled to a host bus which in turn is coupled to an expansion bus through a bus controller. Each CPU board includes a processor connected to a cache system including a cache controller and cache memory. The cache system interfaces to the host bus through address and data buffers controlled by cache interface logic. Distributed system peripheral (DSP) logic comprising various ports, timers, and interrupt controller logic is coupled to the cache system, data buffers, and cache interface logic by a local I/O bus. The computer system supports various areas of concurrent operation, including concurrent local I/O cycles, host bus snoop cycles and CPU requests, as well as concurrent expansion bus reads with snooped host bus cycles.Other References
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