Nonvolatile semiconductor memory circuit with high speed read-out
Patent 5350938 Issued on September 27, 1994. Estimated Expiration Date: 
September 27, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 27, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3893085 High performance electrically alterable read-only memory (EAROM) High speed, nonvolatile, electrically erasable memory cell and system Patent #: 4435790 InventorsApplicationNo. 721702 filed on 06/26/1991US Classes:257/378, Combined with bipolar transistor257/316, With additional contacted control electrode257/E27.103, Electrically programmable ROM (EPO)365/185.05, Particular connection365/185.12, Parallel row lines (e.g., page mode)365/185.18Particular biasingExaminersPrimary: Limanek, Robert P.Attorney, Agent or FirmForeign Patent References
International ClassH01L 029/68Foreign Application Priority Data1990-06-27 JPAbstractA memory cell transistor includes a semiconductor substrate, a N-type source region, a N-type drain region, a control gate and a P+ -type emitter region, which is formed in the surface region of the drain region. An insulating film overlies the source region, the drain region, the emitter region, and the control gate. A contact hole is formed in the insulating film so that the surface of the emitter region is exposed. An emitter electrode is formed in and around the contact hole. A PNP vertical bipolar transistor is constituted by the semiconductor substrate serving as a collector region, a P+ -type buried layer serving as a collector contact, and the drain region serving as a base region.Field of SearchBioplar and FET | |
