U.S. patents available from 1976 to present.
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High-resolution lithography and semiconductor device manufacturing method

Patent 5350485 Issued on September 27, 1994. Estimated Expiration Date: Icon_subject January 26, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

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Inventors

Assignee

Application

No. 009012 filed on 01/26/1993

US Classes:

216/13, FORMING OR TREATING ELECTRICAL CONDUCTOR ARTICLE (E.G., CIRCUIT, ETC.)216/47, Mask is multilayer resist257/E21.03, Electro-lithographic process (EPO)257/E21.031, X-ray lithographic process (EPO)257/E21.314, Using mask (EPO)430/313, With formation of resist image, and etching of substrate or material deposition430/323, Including etching substrate430/325Post image treatment to produce elevated pattern

Examiners

Primary: Dang, Thi

Attorney, Agent or Firm

International Class

H01L 021/00

Foreign Application Priority Data

1992-01-28 JP

Abstract

A lithographic method for forming a mask pattern is useful for etching wiring or insulator layers on a substrate. A catalyst generation layer and a latent image formation layer are formed on the target layer prior to application of actinic radiation to activate a catalyst in the catalyst generation layer in accordance with a predetermined pattern. The activated catalyst diffuses into the latent image formation layer to form a latent image, which then serves as a mask pattern for etching the catalyst generation layer, latent image formation layer and target layer. The catalyst generation layer may be formed prior to the latent image formation layer, or vice versa. In another embodiment, the catalyst generation layer is formed prior to the radiation step, but the latent image formation layer is formed after application of the actinic radiation.

Other References

  • Schellekens et al., "Single Level Dry Developable Resist Systems, Based on Gas Phase Silylation", SPIE, vol. 1086, Advances in Resist Technology and Processing VI, 1989, pp. 220-22
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