Run length limited encoding/decoding system for low power disk drives
October 31, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesData encoding method and system employing two-thirds code rate with full word look-ahead Method and apparatus for generating a noiseless sliding block code for a (1,7) channel with rate 2/3 Apparatus for encoding unconstrained data onto a (1,7) format with rate 2/3 Arrangement for encoding and decoding information signals Synchronization-promoting data coding method Integrated encoder decoder for variable length, zero run length limited codes Method and apparatus for converting a run length limited code Method and apparatus for processing digital signals prior to recording Variable-length coding/decoding device Binary data encoding and decoding using a rate 2/5 (2,18,2) code Patent #: 5173694 InventorApplicationNo. 786334 filed on 10/31/1991US Classes:341/59, To or from run length limited codes341/57, Binary to or from ternary341/100, Serial to parallel341/101, Parallel to serial360/41, Nonreturn to zero360/51Data clockingExaminersPrimary: Logan, Sharon D.Attorney, Agent or FirmInternational ClassesH03M 007/46H03M 007/20 AbstractThe run length limited encoding/decoding system of this invention includes a clock swap logic circuit, a read reference clock multiplexer circuit, a write clock skip logic circuit, an encoder start logic circuit, an encoder circuit, a read clock skip logic circuit, a decoder start logic circuit, a decoder circuit, an input data buffer and a three-state output data buffer. The encoder circuit includes a deserializer for receiving serial data from a disk controller and blocking the data into m bit words. Each m bit data word is supplied directly to an encoding combinatorial logic circuit which in turn generates an n bit code word. The n bit code word is loaded in a serializer and serially transmitted out of the serializer. The decoder circuit includes a deserializer/serializer and a decoding combinatorial logic circuit. The deserializer/serializer receives a serial stream of encoded data and converts the data into n bit code words. Each n bit code word is loaded directly into the decoding combinatorial logic circuit which in turn generates an m bit data word. The m bit data word is loaded into the deserializer/serializer so that as the next n bit code word is serially loaded in the deserializer/serializer, the m bit data worded is serially moved out of the deserializer/serializer.Other References
Field of SearchTo or from run length limited codesDIGITAL CODE TO DIGITAL CODE CONVERTERS Adaptive coding To or from particular bit symbol Bit represented by pulse width Bit represented by discrete frequency Substituting specified bit combinations for other prescribed bit combinations To or from multi-level codes Binary to or from ternary Serial to parallel Parallel to serial To or from minimum d.c. level codes | |
