Flip-flop with identical propagation delay in clock pass through mode and in normal operation
Variable frequency clock for a computer system
State machine architecture providing increased resolution of output timing Patent #: 5159278
ApplicationNo. 028092 filed on 03/08/1993
US Classes:327/141, Synchronizing327/203, Including field-effect transistor327/409Push-pull circuit
ExaminersPrimary: Callahan, Timothy P.
Assistant: Riley, Shawn
Attorney, Agent or Firm
International ClassH03K 005/135
AbstractA circuit having a data path with a programmable clock-to-output delay time (tco). The circuit includes a master-slave flip-flop and selection/predriver logic circuitry whereby two select inputs can program the circuit into one of three different modes of operation. In a data-in mode, the input data is directly connected to the output driver, bypassing the flip-flop. In a fast mode, the circuit tco is reduced such that a higher frequency clock may be used. For low noise operation, the fast mode may be turned off to put the circuit in the regular mode, allowing the circuit to run at lower clock frequencies.