Multiplier tree using nine-to-three adders
Patent 5347482 Issued on September 13, 1994. Estimated Expiration Date: 
December 14, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 14, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesVector multiplier having parallel carry save adder trees Performing binary multiplication using minimal path algorithm Floating point arithmetic two cycle data flow High speed digital computing system Patent #: 5132921 InventorAssigneeApplicationNo. 990627 filed on 12/14/1992US Classes:708/625, Binary708/708Carry-save addersExaminersPrimary: Mai, Tan V.Attorney, Agent or FirmInternational ClassG06F 007/52AbstractA multiplier tree sums the partial products of a multiplication operation, employing a regular hierarchical arrangement of bit adders that accept nine initial inputs and a carry input and produce three outputs and a carry output. The regularity of the structure of the bit adder allows it be used to form an array of bit adders to sum twenty-seven input bits and ten carry input bits to produce three output bits and ten carry outputs bits. These bit adders form the basis of the multiplier tree. The multiplier tree using this structure can sum the partial products from a 52 to 54 bit multiply operation in no more adder delays than a Wallace tree, but with a more regular structure. A method for reducing nine input signals to three output signals segregates the input signals into sets of signals and combines them into reduced sets of logically equivalent signals.Other References
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