Distributed memory architecture for a configurable logic array and method for using distributed memory
August 30, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMemory device Soft programmable logic array Dynamically reconfigurable array logic Semiconductor memory having selectively activated blocks including CMOS sense amplifiers System for programming graphically a programmable, asynchronous logic cell and array Programmable interconnect architecture Programmable logic array having a changeable logic structure Write-read circuit Erasable programmable read only memory device Programmable logic device configurable input/output cell InventorsApplicationNo. 387566 filed on 07/28/1989US Classes:716/16, PLA, PLD, FPGA, OR MCM326/40, With flip-flop or sequential device716/17Programmable integrated circuit (e.g., basic cell, standard cell, macrocell)ExaminersPrimary: Ramirez, Ellis B.Attorney, Agent or FirmForeign Patent References
International ClassesG06F 007/38H03K 019/00 AbstractAdditional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.Other References
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