System and method for accessing memory connected to different bus and requesting subsystem
Fault tolerant digital data processor with improved input/output controller
Controller with clocking device controlling first and second state machine controller which generate different control signals for different set of devices
Computer system speed control at continuous processor speed
Data transfer controller incorporating direct memory access channels and address mapped input/output windows
Two-level priority arbiter generating a request to the second level before first-level arbitration is completed
Method and apparatus for suspending and restarting a bus cycle
CPU-bus controller for accomplishing transfer operations between a controller and devices coupled to an input/output bus
High performance asynchronous bus interface
ApplicationNo. 771297 filed on 10/04/1991
US Classes:710/105, Protocol713/400SYNCHRONIZATION OF CLOCK OR TIMING SIGNALS, DATA, OR PULSES
ExaminersPrimary: Lee, Thomas C.
Assistant: Harrity, Paul
Attorney, Agent or Firm
International ClassesG06F 013/42
AbstractA processing unit tightly couples to a system bus which utilizes a split cycle bus protocol and includes a local memory which is accessible from such bus. The local memory couples to a high speed synchronous bus which operates according to a predetermined bus protocol. The processing unit includes a state machine which couples to the high speed synchronous bus and to the asynchronous system bus. The state machine emulates the predetermined bus synchronous protocol in transferring commands issued to the local memory from the system bus which uses the split cycle protocol.