U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method and apparatus for providing a two conductor serial bus

Patent 5341480 Issued on August 23, 1994. Estimated Expiration Date: Icon_subject April 9, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Loop configured data transmission system
Patent #: 4195351
Issued on: 03/25/1980
Inventor: Barner ,   et al.

Two-wire bus-system comprising a clock wire and a data wire for interconnecting a number of stations
Patent #: 4689740
Issued on: 08/25/1987
Inventor: Moelands ,   et al.

Serial bus interface system for data communication using two-wire line as clock bus and data bus
Patent #: 4847867
Issued on: 07/11/1989
Inventor: Nasu ,   et al.

High capacity communication system over collision-type channels
Patent #: 4899143
Issued on: 02/06/1990
Inventor: Gopinath, et al.

Procedure and apparatus for transmitting binary messages in a serial communication bus
Patent #: 5063561
Issued on: 11/05/1991
Inventor: Kimmo

Bus device which abstains from round robin arbitration
Patent #: 5119292
Issued on: 06/02/1992
Inventor: Baker, et al.

Application specific integrated circuit for a serial data bus
Patent #: 5175750
Issued on: 12/29/1992
Inventor: Donovan, et al.

Dynamic bus arbitration with concurrent same bus granting every cycle Patent #: 5195185
Issued on: 03/16/1993
Inventor: Marenin

Inventors

Assignee

Application

No. 866816 filed on 04/09/1992

US Classes:

710/107Bus access regulation

Examiners

Primary: Shaw, Dale M.
Assistant: Dinh, D.

Attorney, Agent or Firm

International Classes

G06F 013/00
G06F 013/36
G06F 013/368
G06F 013/376

Abstract

A method for rapidly transferring serial data in a two conductor busing arrangement in which one conductor is utilized to transfer data and the other conductor is utilized to transfer clock signals, and in which a plurality of components are connected to the two conductors, at least one of which is capable of acting as a bus master including the steps of providing clock signals on the clock conductor which are active on both edges, placing a special signal on the data conductor to indicate the start of an operation, placing address data on the data conductor to indicate an address on the data conductor, placing data on the data conductor to indicate the type of transfer to be made, acknowledging the receipt of the address by a component being addressed, transferring data on the data conductor, placing a special signal on the data conductor to indicate the end of the data transfer, transferring a signal indicating a parity count, and placing another special signal on the data conductor to indicate the end of the operation.

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