U.S. patents available from 1976 to present.
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Floating point arithmetic unit using modified Newton-Raphson technique for division and square root

Patent 5341321 Issued on August 23, 1994. Estimated Expiration Date: Icon_subject May 5, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Floating point operation unit in division and square root operations
Patent #: 4999801
Issued on: 03/12/1991
Inventor: Katsuno

Floating point arithmetic two cycle data flow
Patent #: 4999802
Issued on: 03/12/1991
Inventor: Cocanougher, et al.

Method and apparatus for performing mathematical functions using polynomial approximation and a rectangular aspect ratio multiplier
Patent #: 5042001
Issued on: 08/20/1991
Inventor: Brightman, et al.

Machine method to perform newton iterations for reciprocal square roots
Patent #: 5157624
Issued on: 10/20/1992
Inventor: Hesson

Machine method to perform newton iterations for reciprocals Patent #: 5220524
Issued on: 06/15/1993
Inventor: Hesson

Inventors

Application

No. 058164 filed on 05/05/1993

US Classes:

708/500, Evaluation of root708/504Division

Examiners

Primary: Mai, Tan V.

Foreign Patent References

  • 0111587 EP 06/13/1984
  • 0166999 EP 01/13/1986
  • 0377992 EP 07/13/1990

International Class

G06F 007/38

Abstract

A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton-Raphson method. The modified form of the Newton-Raphson method is used in place of the final iteration of the conventional Newton-Raphson so as to compute high precision approximated results with a substantial improvement in speed. The invention computes approximated results faster and simplifies hardware requirements because no multiplications of numbers of the precision of the result are required.

Other References

  • Chai et al., "A 120 MFLOPS CMOS Floating-Point Processor", IEEE 1991 Custom Integrated Circuits Conference, pp. 15.1.1-15.1.4
  • Waser et al., "Introduction to Arithmetic for Digital Systems Designers", Holt, Rinehart and Winston, pp. 193-211
  • Karp, A., "Speeding up N-body Calculations on Machines without Hardware Square Root", Document No. G320-3565, IBM Scientific Center, pp. 1-7, Apr. 27, 1992
  • Cody et al., "Software Manual for the Elementary Functions", Prentice-Hall, 1980, Chapter 4, pp. 17-34
  • Markstein, P. W., "Computation of Elementary Functions of the IBM RISC System/6000 Processor", IBM Journal of Research and Development, vol. 34, No. 1, Jan. 1990, pp. 111-119
  • Darley et al., "The TMS390C602A Floating-Point Coprocessor for Sparc Systems", IEEE Micro, Jun. 1990, pp. 36-4
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