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US Patent 5341315 - Test pattern generation device

US Patent Issued on August 23, 1994
Estimated Patent Expiration Date: Icon_subject March 13, 2012Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
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Abstract

A test pattern generation device for producing test pattern signals for testing a preselected digital circuit includes a dominant pattern signal generator and a subservient pattern signal generator. When a first dominant pattern signal (0,0,0,0,0) is generated, five subservient pattern signals (1,0,0,0,0), (0,1,0,0,0), (0,0,1,0,0), (0,0,0,1,0) and (0,0,0,0,1) are generated, each being unit Hamming distance from the dominant pattern signal. The subservient pattern signals are sequentially applied to a simulator carrying a hypothetical digital circuit for producing a controllability cost CCOf and a continuous cyclic logic value CVf at a preselected line Gf in the digital circuit for each subservient pattern signal. A cost generator produces an evaluation cost CTf by the use of the controllability cost CCOf and the continuous cyclic logic value CVf for each subservient pattern signal. A selector selects from the set of subservient pattern signals a subservient pattern signal that produced a minimum evaluation cost CTf, test pattern memory stores the selected subservient pattern signal as one test pattern and assigns the selected subservient pattern signal as a next dominant pattern signal in a next cycle operation.

Other References

  • "An Engineering Approach To Digital Design", William I. Fletcher, Prentice-Hall Inc 1980, pp. 2-8
  • "A Simulation-Based Method for Generating Tests for Sequential Circuits", Cheng et al., IEEE Transactions on Computers, vol. 39 No. 12, Dec. 1990, pp. 1456-1463
  • "Smart and Fast: Test Gen. for ULSI Scandesign Circuits" by M. Abromovici et al. pp. 43-54 (Aug., 1986)
  • "A Sey. Circuit . . . Simulation" by K. T. Cheng et al., pp. 24-29 (1988 IEEE)
  • "A Backtrackless Test Generation Method for Combinational Circuits", Ikeda et al., Oct. 25, 1989, pp. 83-87, English Abstract Only
  • "Method for Preparing a Logic Function Table of a Flip-Flop", Matsushita Electrical Industries Co. Ltd., Niwa et al., Mar. 25, 1991, pp. 1-2 with English Translatio

Inventors

Assignee

Application

No. 850877 filed on 03/13/1992

US Classes:

714/738, Including test pattern generator714/32Particular stimulus creation

Examiners

Primary: Harvey, Jack B.
Assistant: Sjamber, Eric W.

Attorney, Agent or Firm

US Patent References

3961250, Logic network test system with simulator oriented fault test generator
Issued on: 06/01/1976
Inventor: Snethen
4672307Simplified delay testing for LSI circuit faults
Issued on: 06/09/1987
Inventor: Breuer ,   et al.

Foreign Patent References

  • 0342787 EP. 04/21/1989

International Class

G01R 031/28

Foreign Application Priority Data

1991-03-14 JP

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