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US Patent 5341315 - Test pattern generation device
US Patent Issued on August 23, 1994
Estimated Patent Expiration Date:
March 13, 2012Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
March 13, 2012Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA test pattern generation device for producing test pattern signals for testing a preselected digital circuit includes a dominant pattern signal generator and a subservient pattern signal generator. When a first dominant pattern signal (0,0,0,0,0) is generated, five subservient pattern signals (1,0,0,0,0), (0,1,0,0,0), (0,0,1,0,0), (0,0,0,1,0) and (0,0,0,0,1) are generated, each being unit Hamming distance from the dominant pattern signal. The subservient pattern signals are sequentially applied to a simulator carrying a hypothetical digital circuit for producing a controllability cost CCOf and a continuous cyclic logic value CVf at a preselected line Gf in the digital circuit for each subservient pattern signal. A cost generator produces an evaluation cost CTf by the use of the controllability cost CCOf and the continuous cyclic logic value CVf for each subservient pattern signal. A selector selects from the set of subservient pattern signals a subservient pattern signal that produced a minimum evaluation cost CTf, test pattern memory stores the selected subservient pattern signal as one test pattern and assigns the selected subservient pattern signal as a next dominant pattern signal in a next cycle operation.Other References
| InventorsAssigneeApplicationNo. 850877 filed on 03/13/1992US Classes:714/738, Including test pattern generator714/32Particular stimulus creationExaminersPrimary: Harvey, Jack B.Assistant: Sjamber, Eric W. Attorney, Agent or FirmUS Patent References3961250, Logic network test system with simulator oriented fault test generatorIssued on: 06/01/1976 Inventor: Snethen4672307Simplified delay testing for LSI circuit faults Issued on: 06/09/1987 Inventor: Breuer , et al. Foreign Patent References
International ClassG01R 031/28Foreign Application Priority Data1991-03-14 JP |
