Flexible configuration logic array block for programmable logic devices
Patent 5341044 Issued on August 23, 1994. Estimated Expiration Date: 
April 19, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 19, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProgrammable logic array device using EPROM technology Prom with programmable output structures Programmable logic device with global and local product terms Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix High-density erasable programmable logic device architecture using multiplexer interconnections Patent #: 5268598 InventorsApplicationNo. 049064 filed on 04/19/1993US Classes:326/41, Significant integrated structure, layout, or layout interconnections326/39, Array (e.g., PLA, PAL, PLD, etc.)340/14.3ProgrammableExaminersPrimary: Westin, Edward P.Assistant: Sanders, Andrew Attorney, Agent or FirmInternational ClassH03K 019/173AbstractA programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.Other References
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