Method and apparatus for verifying the design of digital electronic components
EPROM emulator for selectively simulating a variety of different paging EPROMs in a test circuit
Method of using electronically reconfigurable logic circuits
Testing of integrated circuits using clock bursts
Apparatus for emulation of electronic hardware system
Test device for an electronic chip
ApplicationNo. 911846 filed on 07/10/1992
US Classes:716/4, Testing or evaluating702/117Of circuit
ExaminersPrimary: Harvey, Jack B.
Assistant: Choi, Jacob Y.
Attorney, Agent or Firm
International ClassG06G 007/62
AbstractA technique for testing the performance of a target electronic system ultimately employing an ASIC comprising a core cell and surrounding logic, using an inchoate (designed, but not yet fabricated) ASIC on an interim basis. In one embodiment, a Q-part, or qualification part, which is essentially a bond-out of the core cell, is used in conjunction with programmable logic devices configured to perform the function of the surrounding logic. The Q-part and programmable logic are interconnected on a pod, and plugged into an interim version of a target electronic system. In another embodiment, the Q-part is software-simulated and interconnected on the pod to programmable logic devices. The programmable logic devices may be programmed either on-pod or off-pod, and signals incident to the operation of the pod plugged into the interim electronic system can be monitored and controlled.