Parallel pipelined instruction processing system for very long instruction word
July 26, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMicrocomputer with branch on bit set/clear instructions Pipelined digital processor arranged for conditional operation System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses Branching control system Pipeline microcomputer having branch instruction detector and bus controller for producing and carrying branch destination address prior to instruction execution System for calculating branch destination address based upon address mode bit in operand before executing an instruction which changes the address mode and branching Patent #: 5142630 InventorsAssigneeApplicationNo. 682085 filed on 04/08/1991US Classes:712/241, Loop execution712/24, Long instruction word712/215, Simultaneous issuance of multiple instructions712/234, Conditional branching717/149For a parallel or multiprocessor systemExaminersPrimary: Lall, Parshotam S.Assistant: Vu, Viet D. Attorney, Agent or FirmForeign Patent References
International ClassesG06F 009/38G06F 007/00 Foreign Application Priority Data1990-04-06 JPAbstractA parallel pipelined instruction processing system for executing a plurality of instructions in parallel without no branch delay, comprises a instruction block fetch unit for fetching an instruction block including at least one instruction field and one branch instruction field, at least one instruction execution unit receiving an instruction included in the instruction field of the instruction block held in the instruction block fetch unit and for executing the received instruction, and a branch instruction execution unit receiving a branch instruction included in the branch instruction field of the instruction block held in the instruction block fetch unit and for executing a processing for the received branch instruction. The branch instruction execution unit includes an operand fetch circuit receiving the branch instruction included in the branch instruction field of the fetched instruction block for fetching, from a data register group, an operand to be used for the received branch instruction, and an address generation circuit receiving the branch instruction included in the branch instruction field of the fetched instruction block and for simultaneously generating a next address of an instruction to be next fetched and a branch destination address for the received branch instruction. The address generation circuit operates to output one of the next address and the branch destination address on the basis of the content of the operand fetch circuit.Other References
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